1. Field of the Invention
The present invention relates to a data processor, and more specifically to a status register apparatus for use in a microprocessor.
2. Description of Related Art
In general, a status register apparatus provided in a microprocessor includes a plurality of control information registers, each being adapted to hold one item of control information inherent to the control information register.
Conventionally, a control word of a microprocessor which is inherent data for setting the status registers is constituted in such a manner that each bit of the control word is assigned to one corresponding control information register. Therefore, it is possible to simultaneously set a plurality of items of control information by means of the control word.
Referring to FIG. 1, there is shown a typical relation between a conventional control word and a virtual mode flag and a cache enable flag, these flags being typical control information registers in the status register apparatus of the microprocessor. The virtual mode flag is for switching between a real address mode of the microprocessor and a virtual address mode for a virtual memory function. This virtual mode flag is assigned to a "No.3" bit of the control word. The cache enable flag is for controlling whether or not an internal cache memory of the microprocessor is used. This cache enable flag is assigned to a "No.2" bit of the control word. In the example shown, since the control word is composed of 8 bits, the control word can be allocated to eight control information registers at maximum. When an operator of the microprocessor rewrites the cache enable flag, the control word is read out from the status register apparatus, and the "No. 2" bit of the read-out control word is modified by means of, for example, an logical product operation, and thereafter, the modified control word is rewritten into the status register apparatus by activating a write signal for the status register apparatus. As a result, the cache enable flag is rewritten.
Thus, the control information register for the cache enable flag can be written by setting a desired value to a corresponding "No.2" bit of the control word, and by writing the corresponding "No.2" bit of the control word having the desired value into the control information register when the write signal is active. Similarly, the control information register for the virtual mode flag can be written by setting a desired value to a corresponding "No.3" bit of the control word, and by writing the corresponding "No.3" bit of the control word having the desired value into the control information register when the write signal is active. In other words, when the write signal is active, all bits or allocated bits of the control words are written into corresponding control information registers. On the other hand, contents of the respective control information registers are maintained by maintaining the write signal in an inaction condition.
On the other hand, the status register apparatus of the conventional microprocessor has been mainly such that the respective control information registers hold control information of the system itself or are allocated to flags indicative of an operation condition of the microprocessor. Therefore, if the status register apparatus is erroneously set, there is a danger that it might cause the system to malfunction, or might damage the system. In the conventional status register apparatus there is a possibility that the status register apparatus might be erroneously set. For example, although only the cache enable flag should be rewritten, if not only the "No.2" bit of the control word corresponding to the cache enable flag but also the "No.3" bit of the control word corresponding to the virtual mode flag were modified, when the write signal becomes active and the cache enable flag is properly rewritten the virtual mode flag might be erroneously rewritten, with the result that the system would cause a "program run away".